In manufacturing of semiconductor devices, a slice of semiconductor material has applied on one of its surfaces a relatively thin layer of an insulating film. A layer of photo-resist material is then spun onto the insulating layer and is subsequently exposed to ultraviolet light through a mask having openings corresponding to those areas on this semiconductor slice where it is desired, for example, to generate semiconductor junctions. This application deals primarily with a process of etching silicon and the manufacturing of the mask through which exposure is made to the photo-resist material.
Silicon has been shown to be an excellent material for use as a see-through photomask layer when deposited as a thin film on glass. One method of depositing silicon currently in use is the chemical vapor deposition from silane or plasma promoted chemical vapor deposition. Another method of depositing silicon is by ordinary sputtering or evaporating using electron beam melting. In order to make a mask, the silicon material is deposited on a glass substrate, thereafter a portion of the silicon has to be removed to define the pattern of the mask.
To remove the silicon material, a photo-resist material may be applied there over and then portions thereof removed to form a particular pattern. Thereafter the silicon material in the exposed areas is also removed. The material can be removed by a number of processes, one of which is a plasma process utilizing halocarbon-oxygen gas mixtures such as those disclosed in U.S. Pat. 3,806,365. However, there are some disadvantages using a technique as described, such as physical degradation of the photo-resist etch mask and undercutting of the silicon material, both of which may impair the line/line resolution of the mask. Present silicon etch techniques use either acid wet etch or dry RF plasma etch using halocarbon mixtures disclosed in above U.S. Pat. No. 3,806,365 tend to produce nonuniform results in a manufacturing operation. Silicon lead dimensions are a critical factor in defining the electrical characteristics of a CCD or silicon gate device. Ability to define closely spaced geometries without significant reduction in lead width (undercut) is a key for high density MOS/LSI circuits.
A gas plasma vapor etching process is disclosed in U.S. Pat. No. 3,615,456 in which a gas containing chlorine is used, however the gas is used to detect pinholes, polish the surfaces of a semiconductor device or etch break lines.
Accordingly it is an object and feature of the present invention to provide an improved process utilizing materials that overcome the aforementioned problems and provide uniform etching without undercutting to provide an efficient process for removing the silicon material in forming silicon masks, connecting leads and semiconductor devices which utilize silicon and require the etching thereof. This technique is anticipated to have increased application in high density MOS/LSI such as 4K, 16K, 64K RAM techniques.